Enforcing Worst-Case Behavior During Transmit Channel Analysis

ABSTRACT

Techniques for analyzing the signal integrity of a channel by enforcing a worst-case behavior during the analysis are presented. Initially a channels response to an input bit sequence, followed by a test bit sequence is simulated. Subsequently, a pulse response is extracted from the simulated channel response. A worst-case pattern bit sequence is then derived from the extracted pulse sequence and the channels response to the worst-case pattern bit sequence is simulated. In further implementations, the channels response to the worst-case pattern bit sequence is displayed for a user.

RELATED APPLICATIONS

This application is a continuation of and claims priority under 35 U.S.C. §120 to U.S. patent application Ser. No. 12/363,354, entitled “Generating Worst-Case Test Sequences for Non-Linearly Driven Channels,” filed on Jan. 30, 2009, which application is a continuation of and claims priority under 35 U.S.C. §120 to U.S. patent application Ser. No. 12/150,658, entitled “Generating Test Sequences for Circuit Channels Exhibiting Duty-Cycle Distortion,” filed on Apr. 29, 2008, which application is a continuation of and claims priority under 35 U.S.C. §120 to U.S. patent application Ser. No. 11/880,354, entitled “Generating Transmission-Code Compliant Test Sequences”, filed on Jul. 19, 2007 and further claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 60/933,807, entitled “Worst-Case pattern Generation for a Linear Channel in Cases of Bit Sequences with Duty-Cycle Distortion”, filed on Jun. 8, 2007, which application further claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 60/927,163, entitled “Worst-Case Pattern Generation for Linear Signal Channels,” filed on May 1, 2007. This application further claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 61/249,973 entitled “Analysis of Serial Channel with Nonlinear Non-Time-Invariant Behavior by the Worst Case ISI/Crosstalk Enforcement,” filed on Oct. 8, 2010. Each of U.S. Provisional Patent Application Nos. 60/933,807, 60/927,163, and 61/249,973 as well as each of U.S. patent application Ser. Nos. 11/880,354, 12/150,658, and 12/363,354 is incorporated entirely herein by reference.

FIELD OF THE INVENTION

This invention relates to the field of electronic design. Various implementations of the invention are applicable to analyzing non-linear-time-invariant transmit channels by enforcing a worst-case behavior in the channel.

BACKGROUND OF THE INVENTION

Modern digital electronic circuits and systems transmit or convey sequences of binary values, commonly referred to as bit sequences or digital signals. These bit sequences are often conveyed as voltage waveforms, wherein the voltage amplitude for a given time period or bit, corresponds to a binary logic value at that same time period. Accordingly, a digital signal appears as a voltage waveform in the signal lines and transmission channels of electronic systems. As a digital signal is transmitted through a circuit, various effects may cause the signal to degrade, often to the point that errors occur. Errors within a digital signal may be quantified by a bit error rate. In many instances, the bit error rate of a circuit or signal pathway is defined as the ratio of incorrectly received bits to the total number of bits transmitted. An important consideration in digital electronic design is fidelity, or the quality with which a signal is conveyed. The fidelity of an electronic system is often referred to as signal integrity. Signal integrity has become increasingly important as the speed with which modern devices operate increases while the physical dimensions of the devices shrink. As a result, virtually all modern electronic circuits are designed with signal integrity in mind.

Designers often employ techniques to assist in optimizing the signal integrity of their designs. Various techniques that simulate or predict the signal integrity of pathways used to transmit signals within a circuit are typically employed. In many cases, these techniques are used prior to the circuit ever being manufactured, by, for example, simulating the signal integrity. By adding simulation techniques to the design phase of a devices development, signal integrity problems can often be identified before the device is ever manufactured. For example, simulation tools can assist the designer in accounting for issues that commonly cause signal degradation, such as ringing, crosstalk, noise, ground bounce, or inter-symbol interference.

Integrated circuit (IC) design and printed circuit board (PCB) design are two areas where electronic design automation tools are commonly used to analyze, correct, or prevent signal integrity problems. In particular, the pathways that transmit signals between various components on a printed circuit board or within an integrated circuit, often referred to as channels, may be analyzed for signal integrity problems. For example, the signal integrity of a channel between a driver and a buffer of a printed circuit board (PCB) layout may be analyzed. It may be advantageous for a designer to perform this analysis so that the bit error rate of the channel may be accurately predicted and then subsequent design changes may be made based in part upon this prediction with the intent of reducing the bit error rate prior to manufacturing.

As discussed above, a digital signal is often referred to as a series or sequence of bits. As further stated above, it is often a design goal that the integrity with which a channel transmits a digital signal is greater than a predefined threshold. In order to assist in reaching these design goals, the channel is often tested under its worst possible operating condition. This may be accomplished by generating a digital signal or bit sequence that produces the worst possible signal integrity values for the channel. More particularly, the bit sequence which experiences the greatest distortion or degradation as it is transmitted through the channel is desired. By testing the channel against the “worst-case” bit sequence, designers can optimize the channels signal integrity.

In many cases, signal integrity analysis underestimates or fails to accurately quantify the unwanted effects of inter-symbol interference and crosstalk. As a result, the actual bit error rate of the channel is often higher than what is predicted. Significantly increasing the number of bits used in the simulation process may lead to more accurate estimates of the bit error rate. However, this approach correspondingly adds to the amount of time and resources required to perform the analysis.

SUMMARY OF THE INVENTION

Various implementations of the invention provide methods and apparatuses for analyzing the signal integrity of a channel. Specifically, various implementations provide for the enforcement of worst-case behavior during channel analysis.

In various implementations of the invention, a channel's response to an input bit sequence is simulated. Additionally, a test bit sequence, is simulated. Subsequently, a pulse response is extracted from the simulated response to the test bit sequence. A worst-case pattern bit sequence is then derived from the extracted pulse sequence and the channel's response to the worst-case pattern bit sequence is simulated. In further implementations, the channel's response to the worst-case pattern bit sequence and the input bit sequence is displayed for a user.

With various implementations, at points within a simulation of a channel's response to an input bit sequence, a test bit sequence, is simulated. Then a pulse response is extracted from the simulated response to the test bit sequence. A worst-case pattern bit sequence is then derived from the extracted pulse sequence and the channel's response to the worst-case pattern bit sequence is simulated. In further implementations, the channel's response to the multiple worst-case pattern bit sequences and the input bit sequence is displayed for a user.

With some implementations, a channel's response to an input bit sequence and then a test bit sequence, for both an intended signal and a crosstalk signal, is simulated. Subsequently, pulse responses corresponding to the intended signal and the crosstalk signal are extracted from the simulated channel response. A worst-case pattern bit sequence corresponding to the intended signal and the crosstalk signal is then derived from the extracted pulse responses and the channel's response to the worst-case pattern bit sequences is simulated. In further implementations, the channels response to the worst-case pattern bit sequences is displayed for a user.

These and additional aspects of the invention will be further understood from the following detailed disclosure of illustrative embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be described by way of illustrative embodiments shown in the accompanying drawings in which like references denote similar elements, and in which:

FIG. 1 illustrates a computing system suitable for use in conjunction with the present invention;

FIG. 2A illustrates an eye diagram, showing the signal integrity of a circuit pathway;

FIG. 2B illustrates an eye diagram, showing the signal integrity of a circuit pathway;

FIG. 3 illustrates an electrical system;

FIG. 4A illustrates a portion of the electrical system of FIG. 3, shown in further detail;

FIG. 4B illustrates a portion of the electrical system of FIG. 3, shown in further detail;

FIG. 5 illustrates a method of enforcing worst-case behavior in a transmit channel;

FIG. 6 illustrates a worst-case behavior simulation tool;

FIG. 7 illustrates a bit sequence; and

FIG. 8 illustrates a channel and various inputs and output sequences and responses.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS Introduction

The operations of the disclosed implementations may be described herein in a particular sequential order. However, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the illustrated flow charts and block diagrams typically do not show the various ways in which particular methods can be used in conjunction with other methods.

It should also be noted that the detailed description sometimes uses terms like “generate” to describe the disclosed implementations. Such terms are often high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will often vary depending on the particular implementation.

Furthermore, in various implementations, a mathematical model may be employed to represent an electronic device. For example, a model describing the connectivity of the device, such as, a netlist, might be employed. Those of ordinary skill in the art will appreciate that the models, even mathematical models represent real world physical device designs and real world physical phenomenon corresponding to the operation of the device. Additionally, those of ordinary skill in the art will appreciate that during many electronic design and verification processes, the response of a device design to various signals or inputs is simulated. This simulated response corresponds to the actual physical response the device being modeled would have to these various signals or inputs.

Some of the methods described herein can be implemented by software stored on a computer readable storage medium, or executed on a computer. Accordingly, some of the disclosed methods may be implemented as part of a computer implemented electronic design automation (“EDA”) tool. The selected methods could be executed on a single computer or a computer networked with another computer or computers.

Illustrative Computing Environment

As the techniques of the present invention may be implemented using software instructions, the components and operation of a computer system on which various implementations of the invention may be employed is described. Accordingly, FIG. 1 shows an illustrative computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 having a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (“ROM”) 109 and a random access memory (“RAM”) 111. As will be appreciated by those of ordinary skill in the art, both the ROM 109 and the RAM 111 may store software instructions for execution by the processing unit 105.

The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional devices, such as; a fixed memory storage device 115, for example, a magnetic disk drive; a removable memory storage device 117, for example, a removable solid state disk drive; an optical media device 119, for example, a digital video disk drive; or a removable media device 121, for example, a removable floppy drive. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 123 and one or more output devices 125. The input devices 123 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 125 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 115-125 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-125 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (“USB”) connection.

With some implementations, the computing unit 103 may be directly or indirectly connected to one or more network interfaces 127 for communicating with other devices making up a network. The network interface 127 translates data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (“TCP”) and the Internet protocol (“IP”). Also, the interface 127 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection.

It should be appreciated that the computing device 101 is shown here for illustrative purposes only, and it is not intended to be limiting. Various embodiments of the invention may be implemented using one or more computers that include the components of the computing device 101 illustrated in FIG. 1, which include only a subset of the components illustrated in FIG. 1, or which include an alternate combination of components, including components that are not shown in FIG. 1. For example, various embodiments of the invention may be implemented using a multi-processor computer, a plurality of single and/or multiprocessor computers arranged into a network, or some combination of both.

Illustrative Channel and Response

As indicated above, various implementations of the invention are applicable to analyzing a circuit channel for signal integrity. Particularly, various implementations are applicable to enforcing the worst-case behavior (often quantified as the response or output) of a circuit channel during analysis. For example, traces, vias, or other interconnects between a driver and a receiver in a printed circuit board layout may be analyzed. As introduced above, the signal integrity of a circuit may be quantified by providing an input bit sequence to a channel, identifying the response of the channel to the input bit sequence, and then comparing the response of the channel to the input bit sequence. Any degradation of the bit sequence, as a result of its being transmitted through the channel can then be ascertained. In various implementations, the input bit sequence may be applied to the circuit in a number of different manners, such as, for example, by providing the sequence to a physical prototype of the circuit, by simulating the circuit and providing the sequence to the simulation, or by emulating the circuit, and providing the sequence to the emulation.

The following implementations are described in the context of simulation. However, these implementations, as well as other implementations of the invention, are equally applicable, to analysis via physical prototype, emulation, or other methods or techniques for analyzing signal integrity.

The signal integrity of a channel is often quantified through an “eye” diagram. An eye diagram is created by repeatedly sampling a digital signal, such as, for example, by simulating the signal, and overlaying the various samples onto each other. FIG. 2A illustrates an eye diagram 201, while FIG. 2B illustrates an eye diagram 203. As can be seen in FIG. 2A and FIG. 2B, the eye diagram 201 is undistorted, while the eye diagram 203 contains distortions. An eye diagram may appear distorted, such as the eye diagram 203, due to various electronic effects. For example, noise, timing issues, overshoot, and undershoot will often manifest themselves as amplitude and phase errors within an eye diagram. The amount of distortion is often quantified by an opening in the eye diagram. FIG. 2A illustrates an opening 205 and FIG. 2B illustrates an opening 207.

As stated above, various implementations of the invention are applicable to enforcing the worst-case response of a channel during simulation. It is to be understood that the term “worst-case” does not necessarily refer to the absolute worst possible response, but encompasses responses that cause the output level or voltage level of the channel to be altered from a threshold output level. Additionally, the “worst-case” response may be defined as the response that has a bit error rate greater than a specified ratio. Furthermore, the “worst-case” response may be defined as the response that produces an eye opening in an eye diagram larger or smaller than a predefined percentage.

FIG. 3 illustrates an exemplary electrical system 301, which may be analyzed using various techniques of the present invention. As can be seen in FIG. 3, the electrical system 301 includes a driver 303, a channel 305, and a buffer 307. With various implementations of the invention, the driver 303 may be a non-linear driver. In general, an electrical component exhibits non-linear behavior when the sum of its responses does not equal the sum of its inputs. More particularly, in a linear system the response to the bit sequence ‘010’ summed with the response to the bit sequence ‘001’ would equal the response to the bit sequence ‘011’. The principle of linearity is often explained mathematically as follows. Given a function F wherein Y₁=F(X₁) and Y₂=F(X₂), if X_(s)=X₁+X₂ then Y_(s)=F(X_(s))=Y₁+Y₂. In a non-linear system, the response to the bit sequence ‘011’ may not equal the summed responses to the bit sequences ‘010’ and ‘001’. Employing the same function F, and Y₁, Y₂, and X_(s) defined above, in a non-linear system Y_(s)=F(X_(s))≠Y₁+Y₂.

As can be seen in FIG. 3, the driver 303 includes an input 309 for receiving a digital signal, or d(t). Additionally, the driver 303 and the buffer 307 are connected by the channel 305. When a digital signal d(t) is placed on the driver 303 via the input 309, a response or voltage waveform, or V(t) is seen at the channel 305. The voltage waveform V(t) is often referred to as the driver voltage, or the transmitter voltage. The response of the driver 303 is measurable at a point 311 in the electrical system 301. Additionally, the response of the channel, or W(t), often referred to as the waveform at the receiver, or the receiver voltage, and is measurable at a point 313 in the electrical system 301. Furthermore, as can be seen in FIG. 3, the driver 303, the channel 305, and the buffer 307 are typically connected to a plurality of ground terminals 315.

The electrical system 301 may be transformed and represented as two separate electrical systems, as illustrated by FIG. 4A and FIG. 4B. With various implementations of the invention, it is desirable to perform these transformations. FIG. 4A illustrates a model 401 that may be implemented to find the driver voltage V(t). As can be seen in FIG. 4A, the model 401 includes the driver 303, the input 309, and an element 403. The element 403 represents the admittance (Y(s)) of the channel 305. FIG. 4A further shows an electrical current 405, which represents the driver current I(t). Additionally, as can be seen, the driver 303 and the element 403 are connected to the ground terminals 315. Given a digital signal d(t), the driver voltage V(t) may be determined by employing the model 401, according to the following Equation [1] describing the electrical properties of the model 401.

$\begin{matrix} {{Y(s)} = \frac{I(s)}{V(s)}} & \lbrack 1\rbrack \end{matrix}$

FIG. 4B illustrates a model 407 that may be implemented to determine the receiver voltage W(t). Once the driver voltage V(t) is determined for a given digital signal d(t) and a given driver current I(t), the model 407 may be used to determine the receiver voltage W(t). As can be seen in FIG. 4B, the model 407 includes a current source 405, which represents the driver current I(t). The model 407 further includes an element 409 that represents the channel 305 and may be described by the following function.

$\begin{matrix} {{K(s)} = \frac{W(s)}{V(s)}} & \lbrack 2\rbrack \end{matrix}$

As equation [2] illustrates, the receiver voltage W(t) can be found by employing the above described transformation. According to the theorem of equivalent source, the model 401 and the model 407 of FIG. 4A and FIG. 4B respectively reproduce the electrical system 301 of FIG. 3. As described above, with some implementations of the invention, the driver 303 is a non-linear driver. Accordingly, the model 401 represents a non-linear transformation. With still further implementations, the transformation is also time invariant. More particularly, given the same initial conditions, an input that is shifted in time will produce a response that is shifted in time accordingly.

Enforcing Worst-Case Behavior for a Non-Linearly Non-Time-Invariant Channel

FIG. 5 illustrates a method 501 that may be provided by various implementations of the present invention. As can be seen from this figure, the method 501 includes an operation 503 for simulating the response of a channel to an input sequence, followed by an operation 505 for simulating the response of the channel to a test sequence. Subsequently, an operation 507 is provided for extracting a characteristic response from the simulated response of the channel and an operation 509 for deriving a worst-case pattern sequence. After which, an operation 511 is provided for simulating the response of the channel to the derived worst-case pattern sequence. Additionally, as can be seen, the method 501 provides that, after the operations 503 through 511 have been performed, the method 501 causes the operation 503 to be performed again.

Various implementations of the present invention may be implemented by a worst-case channel analysis tool, such as, for example, the worst-case channel analysis tool 601 shown in FIG. 6. Illustrative applications of the tool 601 are discussed below with reference to FIG. 5 and FIG. 6. As can be seen from FIG. 6, the tool 601 includes a simulator 603, a pulse response extraction module 613 and a worst-case pattern sequence derivation module 615. With some implementations of the invention, the simulator 603 will be separate from the tool 601. The simulator may, for example, be provided by a user of the tool 601.

In some embodiments of the invention, the simulator 603, and the modules 613 and 615, may be implemented as computer executable software instructions stored on a computer-readable media, such as, for example, the system memory 107 of FIG. 1, the fixed memory storage device 115, the removable memory storage device 117, the optical media device 119, or the removable media device 121. As those of ordinary skill in the art can appreciate, for “information,” such as, for example, the simulated response, to be stored on a computer-readable media, the information is inherently stored in a non-transitory fashion.

As stated, the operation 503 simulates a response to an input sequence. This is facilitated by the simulator 603. As can be seen, the simulator 603 includes a simulation module 605, a bit sequence generation module 607, a channel response recordation module 609 and a response display module 611. In some implementations, the bit sequence generation module 607 is employed to generate input sequences to simulate a channel's response. In some implementations, the input bit sequences are clean bit sequence (i.e. no distortions included). Alternatively, the input bit sequences may have some distortion parameters added, such as, for example, jitter, or duty cycle distortion. With some implementations, the bit sequences are generated by a circuit, such as, for example, a linear feedback shift register (LFSR) or a flip-flop. In some implementations, the user specifies whether the bit sequence is to be clean or dirty, and what method is to be used to generate the bit sequence. In alternative implementations, the user supplies the entire input bit sequence, by, for example, providing a bit sequence corresponding to a number of “directed tests.” These generated bit sequences are often referred to herein as “regular” bit sequences.

The simulation module 605 then simulates the channels response to the regular bit sequence. Subsequently, the channel response recordation module 609 records the simulated response. In some implementations, the recorded response is stored on a computer-readable media, such as, for example, the system memory 107 of FIG. 1, the fixed memory storage device 115, the removable memory storage device 117, the optical media device 119, or the removable media device 121. As those of skill in the art can appreciate, for “information,” such as, for example, the simulated response, to be stored on a computer-readable media, the information is inherently stored in a non-transitory fashion.

In some implementations, the operation 503 further causes that the recorded simulated response be displayed for a user by the response display module 611. This may include generating an eye diagram, a bit error rate plot, or an eye contour plot and providing this to a user, such as, for example by displaying it on an optical display device or printing it on a printer.

Once the operation 503 has simulated the response to the regular bit sequences, the operation 505 simulates the response to another bit sequence. This bit sequence is referred to herein as a “test” bit sequence. In some implementations, the operation 503 simulates the response due to the regular bit sequence for a preselected duration, such as, for example, 1,000 bits (i.e. the regular bit sequence is 1,000 bit long). Alternatively, the duration may be 100,000,000 bits long or more. Often, the duration will be specified by a user of the tool 601.

With some implementations, the test bit sequence is a pseudo random bit sequence. In some implementations, the test bit sequence may have the same bit rate as the regular bit sequence. The test bit sequence may be either clean or dirty as described above in relation to the regular bit sequence. However, it is important to note, that the test bit sequence and the regular bit sequence may both be clean, both be dirty, or one may be clean and the other dirty. With various implementations, the response to the test bit sequence is repeatedly simulated. This allows any residual response due to the regular bit sequence to fade.

It is important to note that the operations within the method 501 are performed within the confines of a single “simulation run.” More particularly, as described, the operation 503 simulates the response due to the regular bit sequences and the operations 505 simulates the response due to the test bit sequences. However, a single contiguous simulation is taking place and the operations 503 and 505 merely control the input sequences and various parameters of the simulation, while the system state is preserved between the various simulation operations of the method 501. For example, FIG. 7 shows a bit sequence 701 having a first bit portion 703 and a second portion 705. As can be seen, the first portion 703 corresponds to the regular bit sequence and the second portion 705 corresponds to the test bit sequence, which as stated, may be repeated. This entire bit sequence 701 is applied to the channel during simulation during the method 501.

As stated, the method 501 also includes the operation 507 for extracting the characteristic response from the response of the channel to the test bit sequences. In various implementations, the extracted response is the pulse response of the channel (i.e. its time domain characteristic), and is extracted by the characteristic response extraction module 613. Various techniques for extracting characteristic responses, such as, for example, pulse responses, are discussed in, e.g. Explanation of IEEE 802.3, Clause 68 TWDB,” by Norman L. Swenson et al., ClariPhy Communications, Inc., 5 Jan. 2006, “Standards Compliance Testing of Optical Transmitters Using Software-Based Equalizing Reference receivers,” by Norman L. Swenson et al., Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference, February 2007, and U.S. Provisional Patent Application No. 61/297,728 entitled “Extraction of Timing Characteristics of a Non-Linear Transmit Chanel,” filed Jan. 22, 2010, and naming Vladimir Dmitriev-Zdorov as inventor, which publications and application are each incorporated entirely herein by reference.

Subsequently, the operation 509 derives the worst-case pattern bit sequence from the characteristic response, such as, for example, by utilization of the worst-case pattern sequence derivation module 615. Various techniques for deriving a worst-case pattern bit sequences are described in, e.g. An Accurate and Efficient Analysis Method for Multi-Gb/s Chip-to-Chip Signaling Schemes,” by B. Casper et al., IEEE Symposium on VLSI Circuits, 2002, which article is incorporated entirely herein by reference. Additionally, techniques for deriving worst-case pattern bit sequences are described in U.S. patent application Ser. No. 12/363,354, entitled “Generating Worst-Case Test Sequences for Non-Linearly Driven Channels,” filed on Jan. 30, 2009, U.S. patent application Ser. No. 12/150,658, entitled “Generating Test Sequences for Circuit Channels Exhibiting Duty-Cycle Distortion,” filed on Apr. 29, 2008, and U.S. patent application Ser. No. 11/880,354, entitled “Generating Transmission-Code Compliant Test Sequences”, filed on Jul. 19, 2007, which applications are all incorporated entirely herein by reference, as stated above.

The worst-case pattern bit sequences is often short compared to the regular and test bit sequence. For example, the worst-case pattern bit sequence is often between a few hundred or a few thousand bits long. In the case on linear and time invariant channels, the worst-case pattern bit sequence often produces a response with the most “stressed” (i.e. distorted) eye diagram. In the case of non-linear and non-time-invariant channels, the worst-case pattern bit sequence often produces a response with an eye diagram that is more stressed than normal for comparable length bit sequences.

Once the worst-case pattern bit sequence is derived, the response of the channel to this sequence may be simulated as provided by the operation 511. It is important to note that as the simulation often takes place in software, it is possible to “pause” or “freeze” the simulation and preserve the system state in between simulating the response to the regular bit sequence, the response to the test bit sequence, or the response to the worst-case pattern bit sequence. However, as can be appreciated, the system state is preserved, such as, for example, by being stored in a non-transitory computer-readable medium, during this “freezing,” enabling a contiguous simulation. Referring back to FIG. 7, the bit sequence 701 also has a third bit sequence 707, which corresponds to the worst-case pattern bit sequences and a fourth bit sequence 709, which corresponds to a second regular bit sequence, which is explained below.

In various implementations, the operation 511 causes the simulated response to the worst-case pattern bit sequence to be recorded by the channel response recordation module 609 and displayed to a user by the response display module 611. Once the response to the worst-case pattern bit sequence is simulated, the operation 503 is repeated until an end condition is met. In various implementations the end condition is that a much greater number of bits have been simulated based upon regular bit sequences than other bit sequences.

With some implementations, the method 501 is repeated a number of times. More particularly, the operations 503 through 511 are repeated, such that, every n bits a worst-case pattern bit sequence is simulated by the operation 511. In some implementations, n is 50,000 bits. In alternative implementations, n is 100,000,000 bits or more. Often, n is supplied by the user.

As detailed above, channel responses to regular bit sequences and worst-case pattern bit sequences are simulated, and recorded. Additionally, as stated, various displays of these responses may be generated and provided to a user. A user may, for example, make changes to the channel's design based upon these responses. In some cases, the user may make changes based upon the regular bit sequence responses compared to the worst-case bit sequence response. With some cases, it is advantageous to compare the responses to the first regular bit sequence, the worst case bit sequence, and the second regular bit sequence. In alternative cases, it may be advantageous to compare the responses from multiple applications of regular bit sequences and worst case bit sequences.

Enforcing Worst-Case Behavior for a Non-Linearly Non-Time-Invariant Channel with Crosstalk

Various implementations of the invention may be provided to enforce worst-case behavior in channels with crosstalk. As will be appreciated, crosstalk is where signals transmitted in one channel within a system create unintended effects (e.g. manifest in the channel's response) on signals within another channel in the system. FIG. 8 illustrates a system 801, including a channel 803. As can be seen, the channel 803 includes a signal component 805 and a crosstalk component 807. The method 501 described above may be implemented to simulate worst-case behavior of the system 801. As can be appreciated, the component 805 corresponds to the channel under analysis and the component 807 corresponds to crosstalk from an adjacent channel. In various implementations, the channel 803 can be expanded to account for multiple crosstalk component 807 (not shown).

As described previously in conjunction with FIG. 5, the method 501 includes three modes, regular mode, test mode, and worst-case mode, with the regular mode occurring at the beginning and the end of the method 501. Application of the method 501 to the system will follow the pattern described above except that two bit sequences will be used for each mode. For example, a regular bit sequence for the signal channel 805 and a regular bit sequence for the crosstalk channel 807 will be simulated by the operation 503. As can be seen from FIG. 8, a regular bit sequence 809 and a regular bit sequence 811 are applied to the signal channel 805 and the crosstalk channel 807 respectively. As can be further seen, the combined response 813 can be determined. These responses may add linearly. Alternatively, these responses may combine in a non-linear fashion. Furthermore, as detailed above, the operation 503 may generate a display of the responses, such as, for example, an eye diagram 815.

Similar to the regular bit sequences (i.e. one for each component 805 and 807,) there are two test bit sequence, a test bit sequence 817 for the signal component 805 and a test bit sequence 819 for the crosstalk component 807. The test bit sequences result in the test bit sequence responses 821 when simulated by application of the operation 505. In various implementations, during test mode only the test bit sequence 817 (i.e. the signal component 805 test bit sequence) is provided to the simulator at first. Subsequently, both the test bit sequence 817 and the test bit sequence 819 are provided to the simulator. This results in two test bit sequence responses 821 a and 821 b. The first response 821 a, resulting from simulation with only the test bit sequence 817 does not include crosstalk while the second response 821 b does. The operation 507 can be applied to extract the characteristic response 823 for the signal component 805, which may be determined from the first response 821 a and the characteristic response 825 for the crosstalk component 807, which may be determined from a difference between the first response 821 a and the second response 821 b (i.e. assuming the test bit sequence 817 and the initial system state is the same for both simulations that produce the first response 821 a and the second response 821 b).

From these characteristic responses, worst-case pattern bit sequences 827 and 829 respectively can be derived, as provided by the operation 509 and the worst-case responses simulated by the operation 511, resulting in the worst-case bit sequence response 831 and the eye diagram 833.

As illustrated in conjunction with FIG. 8, the method 505 can be applied to a channel having a signal component and a single crosstalk component. However, as stated, multiple crosstalk components can be accounted for by simply scaling the number of crosstalk components 807, and correspondingly scaling the number of bit sequences and responses accounted for.

CONCLUSION

Although certain devices and methods have been described above in terms of the illustrative embodiments, the person of ordinary skill in the art will recognize that other embodiments, examples, substitutions, modification and alterations are possible. It is intended that the following claims cover such other embodiments, examples, substitutions, modifications and alterations within the spirit and scope of the claims. 

1. A computer-implemented method comprising: receiving an input bit sequence; receiving a test bit sequence; causing the input bit sequence to be applied to a transmit channel; causing the test bit sequence to be applied to the transmit channel; identifying a first output of the transmit channel caused in part by application of the test bit sequence; extracting a characteristic response from the first output; deriving a worst-case pattern bit sequence based in part upon the characteristic response; causing the worst-case pattern bit sequence to be applied to the transmit channel; identifying a second output of the transmit channel caused in part by application of the worst-case pattern bit sequence; and storing the second output to one or more non-transient memory storage locations.
 2. The computer-implemented method recited in claim 1, further comprising: identifying a third output of the transmit channel caused in part by application of the input bit sequence; and storing the third output to one or more non-transient memory storage locations.
 3. The computer implemented method recited in claim 2, wherein storing the second output one or more non-transient memory storage locations comprises: deriving a display of the second output; and causing the display to be presented for a user.
 4. The computer implemented method recited in claim 3, wherein storing the second output one or more non-transient memory storage locations comprises: deriving a display of the third output; and causing the display to be presented for a user.
 5. The computer implemented method recited in claim 3, wherein the display is of a type selected from the group consisting of an eye diagram, an eye contour, and a bit error rate plot.
 6. The computer implemented method recited in claim 1, wherein causing the input bit sequence to be applied to the transmit channel comprises: identifying an end condition; identifying a model of the transmit channel; identifying a simulator; and causing the simulator to simulate the response of the transmit channel to the input bit sequence until the end condition is satisfied.
 7. The computer implemented method recited in claim 6, wherein the end condition is that a preselected number of bits have been applied to the transmit channel.
 8. The computer implemented method recited in claim 7, wherein the preselected number of bits is between 1,000 and 100,000,000.
 9. The computer implemented method recited in claim 1, wherein the test bit sequence is a pseudo random bit sequence.
 10. The computer implemented method recited in claim 1, wherein the characteristic response is a pulse response.
 11. The computer implemented method recited in claim 1, wherein: the worst-case pattern bit sequence has a shorter bit length than the input bit sequence; and the worst-case pattern bit sequence has a shorter bit length than the test bit sequence.
 12. The computer implemented method recited in claim 4, wherein the method acts are repeated.
 13. The computer implemented method recited in claim 12, wherein the number of bits of included in the input bit sequence, the test bit sequence, and the worst-case pattern bit sequence combined is less than 500,000.
 14. The computer implemented method recited in claim 1, wherein: the method act of causing the input bit sequence to be applied to a transmit channel comprises causing a simulator to simulate the response of a transmit channel to the input bit sequence; the method act of causing the bit sequence to be applied to a transmit channel comprises causing a simulator to simulate the response of a transmit channel to the test bit sequence; and the method act of causing the worst-case pattern bit sequence to be applied to a transmit channel comprises causing a simulator to simulate the response of a transmit channel to the worst-case pattern bit sequence.
 15. A computer-implemented method comprising: receiving an input signal bit sequence; receiving an input crosstalk bit sequence; causing the input signal bit sequence to be applied to a transmit channel; causing the input crosstalk bit sequence to be applied to a crosstalk channel; receiving a test signal bit sequence; receiving a test crosstalk bit sequence; causing the test signal bit sequence to be applied to the transmit channel; identifying a first output of the transmit channel caused in part by application of the test signal bit sequence; causing the test signal bit sequence to be applied to the transmit channel; causing the test crosstalk bit sequence to be applied to the crosstalk channel; identifying a second output of the transmit channel caused in part by application of the test signal bit sequence to the transmit channel and the crosstalk bit sequence to the crosstalk channel; extracting a first characteristic response from the first output; extracting a second characteristic response from the second output; deriving a worst-case pattern signal bit sequence based in part upon the first characteristic response; deriving a worst-case pattern crosstalk bit sequence based in part upon the second characteristic response; causing the worst-case pattern signal bit sequence to be applied to the transmit channel; causing the worst-case pattern crosstalk bit sequence to be applied to the crosstalk channel; identifying a third output of the transmit channel caused in part by application of the worst-case pattern signal bit sequence to the transmit channel and the worst-case pattern crosstalk bit sequence to the crosstalk channel; and storing the third output to one or more non-transient memory storage locations.
 16. One or more computer-readable medium for enforcing a worst case response of a transmit channel, the one or more computer-readable medium non-transitorily storing a set of software instructions thereon, the set of software instructions causing a computer to perform a set of operations, the set of operations comprising: receiving an input bit sequence; receiving a test bit sequence; causing the input bit sequence to be applied to a transmit channel; causing the test bit sequence to be applied to the transmit channel; identifying a first output of the transmit channel caused in part by application of the test bit sequence; extracting a characteristic response from the first output; deriving a worst-case pattern bit sequence based in part upon the characteristic response; causing the worst-case pattern bit sequence to be applied to the transmit channel; identifying a second output of the transmit channel caused in part by application of the worst-case pattern bit sequence; and storing the second output to one or more non-transient memory storage locations.
 17. A system for enforcing a worst case response of a transmit channel comprising: a simulation module for simulating a channels response to an input; an input generation module for generating a bit sequence to serve as the input; a response recordation module for capturing and storing the channels response; a response display module for displaying the channels response; a characteristic response extraction module for extracting a characteristic response from the channels response; and a worst-case pattern bit sequence derivation module for deriving a worst-case pattern bit sequence. 